precision analog microcontroller, 12 - bit analog i/o, large memory, arm7tdmi mcu with en hanced irq handler silicon anomaly aduc7124 / aduc7126 rev. b document feedback information furnishe d by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, m a 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2011 - 2014 analog devices, inc. all rights reserved. technical support www.analog.com this anomaly list describes the known bugs, anomalies, and work aro unds for the aduc7124 / aduc7126 microconverter? revision b silicon. the anomalies listed apply to all aduc7124 / aduc7126 packaged material branded as follows: first line aduc7124 or aduc7126 third line b30 analog devices, inc. , is committed, through future silicon revisions, to continuously improve silicon functionality. analog devices tries to ensure that these future silicon revisions remain compatible with your present software/systems by implementing the recommended workarounds outlined here. ad u c7124 / ad u c7126 functionality issues silicon revision identifier kernel revision identifier chip marking silicon status anomaly sheet no. of reported anomalies b 30 all silicon branded b30 released rev. b 7 ad u c7124 / ad u c7126 perormance issues silicon revision identifier kernel revision identifier chip marking silicon status anomaly sheet no. of reported anomalies b 30 all s ilicon branded b30 released rev. b 2
aduc7124/aduc7126 silicon anomaly rev. b | page 2 of 5 functionality issues table 1 . adc conversion conv start edge trigger mode [er001] background adc conversion can be set as conv start falling edge trig ger mode by setting adccon bit 13 and with adccon[2:0] = 000. clearing adccon bit 13 enable s conv start high level trig ger mode. issue adc conversion by conv start edge trig ger mode is not reliable. workaround confi gu re conv start th r ough one pla flip - flop with ulck as its clock. this ensure s that the adc is triggered by conv start when its pulse width is more than 25 ns. this will be fixed in the next revision. related issues none. table 2 . adc conversion pla edge trigger mode [er002] background the adc conversion can be set as pla rising edge trig ger mode by setting adccon bit 13 and with adccon[2:0] = 101. clearing adccon bit 13 enable s pla low level trig ger mode. issue adc conversion by pla edge trig ger mode is not reliable. workaround configu re the pla element output th r ough another pla fli p- flop with ulck as its clock. this ensure s that the adc is triggered by the pla edge when cd is less than 5. thi s will be fixed in the next revision. related issues none. table 3 . disabling i 2 c interface in slave mode when a transfer is in progress [er003] background the i2csen bit (bit 0 in the i2cxscon register) enables/disables the i 2 c slave interface. the i2csbusy bit (bit 6 in the i2cxssta register) indicates whether the i 2 c slave interface is busy. issue if i 2 c slave mode is enabled ( i2cxscon bit 0 = 1) and a transfer is in progress with the master, do not clear i2cxscon bit 0 to 0 t o disable the i 2 c slave interface until the i 2 c busy bit, i2csbusy (bit 6 of i2cxssta), is cleared. when i2cxscon bit 0 is cleared to 0 and i2csbusy is still set, the aduc71 24 / aduc7126 may drive the sdax pins low indefinitely. when this condition occ urs, the ad uc7124/ aduc7126 do not release the sdax pins unless a hardware reset condition occurs. workaround when disabling i 2 c slave mode by writing to the i2csen bit (bit 0 in the i2cxscon register), first set the i2cmen bit (bit 0 in the i2cxmcon register) = 1 to enable master mode. then disable the slave mode by clearing the i2csen bit. finally, clear the i2cmen bit. related issues none. table 4 . operat ion of spi in slave mode [er004 ] background when in spi slave mode, the aduc7124 / aduc7126 expect the number of clock pulses from the master to be divisible by 8 when the chip select ( cs ) pin is low. the internal bit shift counter within the ad uc7124/ aduc7126 is not reset when the chip select pin is deasserted. issue if the number of clocks from the master is not divisible by 8 when the chip select is active, incorrect data may be received or transmitted by the aduc7124 / aduc7126 because the bit sh ift counter will not be at 0 for future transfers. the internal bit shift counter for the transmit or receive buffers can only be reset by a hardware, software, or watchdog reset. workaround always ensure that the number of spi clocks is divisible by 8 wh en the aduc7124 / aduc7126 chip select is active. related issues none.
silicon anomaly aduc7124/aduc7126 rev. b | page 3 of 5 table 5 . timer0 in periodic mode with internal 32 khz clock [er005] background in periodic mode, the internal counter decrements/increments from the value in the load register (t0ld mmr) until zero/full scale and starts again at the value stored in the load register. the value of a counter can be read at any time by accessing its value register (t0val). issue the first timer interrupt occurs only after a full 16 - bit countdown. after the countdown, the t0ld value is copied into t0val as expected. th is issue occurs only when the 32 khz oscillator is serving as the timer source. workaround none. related issues none. table 6 . i 2 c slave not releasing the bus [er006] background when an i 2 c read request happens, if the slaves t x fifo is empty, the slave should nack the masters request. then it should release the bus, allowing the master to generate a stop condition. issue if the slaves t x fifo is loaded with a byte whos msb is 0 just on the rising edge of scl for the ack/nac k, the slave will pull the sda low and hold the line until the device is reset. workaround make sure the t x fifo is always loaded on time by preloading t x fifo in the preceding rx interrupt. related issues none. table 7 . i 2 c clo ck stretch issue [er007] background clock stretching is a feature that allows a device to halt the i 2 c bus temporarily by holding scl low. bit 6 of t he i2cxscon register enables clock stretching in slave mode. bit 3 of t he i2cxmcon register enables clock stretching in master mode. issue writing to i2cxscon bit 6 or to i2cxmcon bit 3 on the rising edge of scl can cause a glitch that may be interpreted by other devices as a real clock edge and might hang the bus. workaround do not enable clock stretching. related issues none.
aduc7124/aduc7126 silicon anomaly rev. b | page 4 of 5 performance issues table 8 . adc and dac reference selection limitation [pr001] background the aduc7124 / aduc7126 provide an on - chip band gap reference of 2.5 v, which can be used for the adc and dacs. this internal reference also appears on the v ref pin. when using the internal reference, a 0.47 f capacitor must be connected from the external v ref pin to agnd to ensure stability and fast response during adc conversions. issue when refcon = 0x00 is set , the internal 2.5 v reference is unstable ; t hat is , when the adc uses the external reference (refcon = 0x00) and the dacs use the internal 2.5 v reference (dacxcon [1:0] = 10), the dac output is unstable. workaround set refcon = 0x00 for the adc to use the external reference, a nd set dacxcon [1:0] = 01 for the dacs to use a different external refer ence from dac ref . related issues none. table 9 . jtag clock limitation [pr002] background the jtag clock speed is limited. issue j tag speed requires tck < uclk/( 2 cd 6) ; that is, tck should be changed according to how the cd ( cp u clock divider ) bits are set. if tck is greater than the limitation, the jtag can not download until the power - on reset ( por ) is at the correct tck speed. workaround the jtag clock speed must be set up manually. the default k ernel setting for the cpu clo ck is cd = 3 (5.22 mhz). therefore , a jtag clock speed limitation of 800 khz or less must be maintained. related issues none .
silicon anomaly aduc7124/aduc7126 rev. b | page 5 of 5 section 1. aduc7124/ aduc7126 functionality issues reference number description status er001 adc conversionconv start edge trigger mode open er002 adc conversionpla edge trigger mode open er003 disabling i 2 c interface in slave mode when a transfer in progress open er004 operation of spi in slave mode open er005 timer0 in periodic mode with an internal 32 khz clock open er006 i 2 c slave not releasing the bus open er007 i 2 c clock stretch issue open section 2. aduc7124/ aduc7126 performance issues reference number description status pr001 adc and dac reference selection limitation open pr002 jtag clock limitation open i 2 c refers to a communications protocol originally developed by philips semiconductors (now nxp semiconductors). ? 2011-2014 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. s09861-0-9/14(b)
|
